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M24128 M24C64 M24C32
128 Kbit, 64 Kbit and 32 Kbit serial IC bus EEPROM
Feature summary
Two-Wire I2C serial interface Supports 400kHz Protocol Single supply voltages (see Table 1 for root part numbers): - 2.5 to 5.5V - 1.8 to 5.5V - 1.7 to 5.5V Write Control Input Byte and Page Write Random And Sequential Read modes Self-Timed programming cycle Automatic address incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Write cycles More than 40-year data retention Packages - ECOPACK(R) (RoHS compliant) Product list
Root part number M24128-BW Supply voltage 2.5 to 5.5V 1.8 to 5.5V 2.5 to 5.5V 1.8 to 5.5V 1.7 to 5.5V 2.5 to 5.5V 1.8 to 5.5V 1.7 to 5.5V
PDIP8 (BN)

SO8 (MN) 150 mil width
Table 1.
Reference M24128
TSSOP8 (DW) 169 mil width
M24128-BR M24C64-W M24C64 M24C64-R M24C64-F M24C32-W M24C32 M24C32-R M24C32-F
UFDFPN8 (MB) 2x3mm (MLP)
October 2006
Rev 9
1/34
www.st.com 1
Contents
M24128, M24C64, M24C32
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.1 2.0.2 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 2.3.2 2.3.3 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 6
2/34
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M24128, M24C64, M24C32
Contents
7 8 9 10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/34
List of tables
M24128, M24C64, M24C32
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating conditions (M24128-BW, M24C64-W, M24C32-W) . . . . . . . . . . . . . . . . . . . . . . 21 Operating conditions (M24128-BR, M24C64-R, M24C32-R) . . . . . . . . . . . . . . . . . . . . . . . 21 Operating conditions (M24C64-F, M24C32-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC characteristics (VCC = 2.5V to 5.5V, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC characteristics (VCC = 2.5V to 5.5V, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics (VCC = 1.8V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics (VCC = 1.7V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC characteristics (VCC = 2.5V to 5.5V, device grades 6 and 3) . . . . . . . . . . . . . . . . . . . . 25 AC characteristics (VCC = 1.8V to 5.5V or VCC = 1.7V to 5.5V) . . . . . . . . . . . . . . . . . . . . . 25 PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, package mechanical data . . . . . . . . . . . . 27 SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 29 UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/34
M24128, M24C64, M24C32
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIP, SO, TSSOP and UFDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 9 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . . . . 27 SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . 28 TSSOP8 - 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 29 UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5/34
Summary description
M24128, M24C64, M24C32
1
Summary description
The M24C32, M24C64 and M24128 devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 4096 x 8 bits, 8192 x 8 bits and 16384 x 8 bits, respectively. In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram
VCC
3 E0-E2 SCL WC
M24128-BW M24128-BR M24C64-W M24C64-R M24C64-F M24C32-W M24C32-R M24C32-F
SDA
VSS
AI01844d
I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
6/34
M24128, M24C64, M24C32 Table 2.
E0, E1, E2 SDA SCL WC VCC VSS
Summary description
Signal names
Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
Figure 2.
DIP, SO, TSSOP and UFDFPN connections
M24128 M24C64 M24C32 1 8 2 7 3 6 4 5
E0 E1 E2 VSS
VCC WC SCL SDA
AI01845e
1. See Package mechanical section for package dimensions, and how to identify pin-1.
7/34
Signal description
M24128, M24C64, M24C32
2
2.0.1
Signal description
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
2.0.2
Serial Data (SDA)
This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated).
2.1
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to VCC or VSS, to establish the Device Select Code as shown in Figure 3. When not connected (left floating), these inputs are read as Low (0,0,0). Figure 3. Device select code
VCC VCC
M24xxx Ei
M24xxx Ei
VSS
VSS
Ai12806
2.2
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.
8/34
M24128, M24C64, M24C32
Signal description
2.3
2.3.1
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 9 and Table 10). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
2.3.2
Internal device reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 9 and Table 10). When VCC has passed the POR threshold, the device is reset and is in Standby Power mode.
2.3.3
Power-down
At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected and in the Standby Power mode (that is there should be no internal Write cycle in progress). Figure 4.
20 Maximum RP value (k) 16 RP 12 8 4 0 10 100 C (pF)
AI01665b
Maximum RP value versus bus parasitic capacitance (C) for an I2C bus
VCC
RP
SDA MASTER fc = 100kHz fc = 400kHz SCL C
C 1000
9/34
Signal description Figure 5. I2C bus protocol
M24128, M24C64, M24C32
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
Table 3.
Device select code
Device Type Identifier(1) b7 b6 0 b5 1 b4 0 Chip Enable Address(2) b3 E2 b2 E1 b1 E0 RW b0 RW
Device Select Code
1
1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 4.
b15
Address most significant byte
b14 b13 b12 b11 b10 b9 b8
Table 5.
b7
Address least significant byte
b6 b5 b4 b3 b2 b1 b0
10/34
M24128, M24C64, M24C32
Memory organization
3
Memory organization
The memory is organized as shown in Figure 6. Figure 6.
WC E0 E1 E2 SCL Control Logic High Voltage Generator
Block diagram
SDA
I/O Shift Register
Address Register and Counter
Data Register
Y Decoder
1 Page
X Decoder
AI06899
11/34
Device operation
M24128, M24C64, M24C32
4
Device operation
The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24C32, M24C64 and M24128 devices are always slaves in all communications.
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle.
4.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.
4.4
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.
12/34
M24128, M24C64, M24C32
Device operation
4.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode. Table 6.
Mode Current Address Read Random Address Read Sequential Read Byte Write
Operating modes
RW bit WC(1) 1 0 1 1 0 X X 1 X X VIL VIL 1 1 32 for M24C64 and M24C32 64 for M24128 reSTART, Device Select, RW = 1 Similar to Current or Random Address Read START, Device Select, RW = 0 Bytes 1 Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address
Page Write
0
START, Device Select, RW = 0
1. X = VIH or VIL.
13/34
Device operation Figure 7.
WC ACK BYTE WRITE START DEV SEL R/W ACK
M24128, M24C64, M24C32 Write mode sequences with WC = 1 (data write inhibited)
ACK
NO ACK DATA IN STOP
BYTE ADDR
BYTE ADDR
WC ACK PAGE WRITE START DEV SEL R/W ACK ACK NO ACK DATA IN 1 DATA IN 2
BYTE ADDR
BYTE ADDR
WC (cont'd) NO ACK PAGE WRITE (cont'd) NO ACK
DATA IN N STOP
AI01120C
14/34
M24128, M24C64, M24C32
Device operation
4.6
Write operations
Following a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data Byte. Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 7. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least Significant Byte (Table 5). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device's internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.
4.7
Byte Write
After the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8.
4.8
Page Write
The Page Write mode allows up to 32 bytes (for the M24C32 and M24C64) or 64 bytes (for the M24128) to be written in a single Write cycle, provided that they are all located in the same 'row' in the memory: that is, the most significant memory address bits (b13-b6 for M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 32 bytes of data (for the M24C32 and M24C64) or 64 bytes of data (for the M24128), each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition.
15/34
Device operation Figure 8.
WC ACK BYTE WRITE START DEV SEL R/W ACK
M24128, M24C64, M24C32 Write mode sequences with WC = 0 (data write enabled)
ACK DATA IN
ACK
BYTE ADDR
BYTE ADDR
WC ACK PAGE WRITE START DEV SEL R/W ACK ACK DATA IN 1 ACK DATA IN 2
BYTE ADDR
BYTE ADDR
WC (cont'd)
ACK PAGE WRITE (cont'd) DATA IN N
ACK
STOP
STOP
AI01106C
16/34
M24128, M24C64, M24C32 Figure 9. Write cycle polling flowchart using ACK
WRITE Cycle in Progress
Device operation
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
4.9
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 17 and Table 18, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: - - - Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
17/34
Device operation Figure 10. Read mode sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP
M24128, M24C64, M24C32
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK
ACK DEV SEL * START
ACK
NO ACK DATA OUT STOP ACK
BYTE ADDR
BYTE ADDR
R/W
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
NO ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL *
ACK
ACK DEV SEL * START
ACK
BYTE ADDR R/W
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
AI01105C
1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.
18/34
M24128, M24C64, M24C32
Device operation
4.10
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device's internal address counter is incremented by one, to point to the next byte address.
4.11
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
4.12
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the Byte.
4.13
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h.
4.14
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode.
19/34
Initial delivery state
M24128, M24C64, M24C32
5
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
6
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7.
Symbol TA TSTG TLEAD VIO VCC VESD
Absolute maximum ratings
Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering PDIP-Specific Lead Temperature during Soldering Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model)(3) -0.50 -0.50 -4000 Min. -40 -65 see note Max. 130 150
(1) (2)
Unit C C C C V V V
260
6.5 6.5 4000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. TLEAD max must not be applied for more than 10s. 3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500, R2=500)
20/34
M24128, M24C64, M24C32
DC and AC parameters
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply Voltage Ambient Operating Temperature (Device Grade 6) Ambient Operating Temperature (Device Grade 3)
Operating conditions (M24128-BW, M24C64-W, M24C32-W)
Parameter Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 9.
Symbol VCC TA
Operating conditions (M24128-BR, M24C64-R, M24C32-R)
Parameter Supply Voltage Ambient Operating Temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 10.
Symbol VCC TA
Operating conditions (M24C64-F, M24C32-F)
Parameter Supply Voltage Ambient Operating Temperature Min. 1.7 -20 Max. 5.5 85 Unit V C
Table 11.
Symbol CL
AC test measurement conditions
Parameter Load Capacitance Input Rise and Fall Times Input Levels Input and Output Timing Reference Levels Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 11. AC test measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
21/34
DC and AC parameters Table 12.
Symbol CIN CIN ZWCL ZWCH tNS
M24128, M24C64, M24C32 Input parameters
Parameter(1),(2) Test Condition Min. Max. 8 6 VIN < 0.3VCC VIN > 0.7VCC 50 500 200 200 Unit pF pF k k ns
Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Pulse width ignored (Input Filter on SCL and SDA)
1. TA = 25C, f = 400kHz 2. Sampled only, not 100% tested.
Table 13.
Symbol ILI ILO ICC ICC0
DC characteristics (VCC = 2.5V to 5.5V, device grade 6)
Parameter Input Leakage Current (SCL, SDA, E2, E1, E0) Output Leakage Current Supply Current (Read) Supply Current (Write) Stand-by Supply Current Test Condition (in addition to those in Table 8) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z 2.5V < VCC < 5.5V, fc=400kHz (rise/fall time < 30ns) During tW, 2.5V < VCC < 5.5V VIN = VSS or VCC, VCC = 5.5V VIN = VSS or VCC, VCC = 2.5V -0.45 0.7VCC IOL = 2.1mA, VCC = 2.5V or IOL = 3mA, VCC = 5.5V Min. Max. 2 2 2 5(1) 5 2 0.3VCC VCC+1 0.4 Unit A A mA mA A A V V V
ICC1 Stand-by Supply Current VIL VIH VOL Input Low Voltage (SDA, SCL, WC) Input High Voltage (SDA, SCL, WC) Output Low Voltage
1. Characterized value, not tested in production.
22/34
M24128, M24C64, M24C32 Table 14.
Symbol ILI ILO ICC ICC0 ICC1 VIL VIH VOL
DC and AC parameters
DC characteristics (VCC = 2.5V to 5.5V, device grade 3)
Parameter Input Leakage Current (SCL, SDA, E2, E1, E0) Output Leakage Current Supply Current (Read) Supply Current (Write) Stand-by Supply Current Input Low Voltage (SDA, SCL, WC) Input High Voltage (SDA, SCL, WC) Output Low Voltage IOL = 2.1mA, VCC = 2.5V or IOL = 3mA, VCC = 5.5V Test Condition (in addition to those in Table 8) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z 2.5V < VCC < 5.5V, fc=400kHz (rise/fall time < 30ns) During tW, 2.5V < VCC < 5.5V VIN = VSS or VCC, 2.5V < VCC < 5.5V -0.45 0.7VCC Min. Max. 2 2 2 5(1) 10 0.3VCC VCC+1 0.4 Unit A A mA mA A V V V
1. Characterized value, not tested in production.
Table 15.
Symbol ILI ILO ICC ICC0 ICC1 VIL VIH VOL
DC characteristics (VCC = 1.8V to 5.5V)
Parameter Input Leakage Current (SCL, SDA, E2, E1, E0) Output Leakage Current Supply Current (Read) Supply Current (Write) Stand-by Supply Current Input Low Voltage (SDA, SCL, WC) Input High Voltage (SDA, SCL, WC) Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V Test Condition (in addition to those in Table 9) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =1.8V, fc = 400kHz (rise/fall time < 30ns) During tW, 1.8V < VCC < 2.5V VIN = VSS or VCC, 1.8V < VCC < 2.5V -0.45 0.7VCC Min. Max. 2 2 0.8 3(1) 1 0.3 VCC VCC+1 0.2 Unit A A mA mA A V V V
1. Characterized value, not tested in production.
23/34
DC and AC parameters Table 16.
Symbol
M24128, M24C64, M24C32 DC characteristics (VCC = 1.7V to 5.5V)(1)
Parameter Test Condition (in addition to those in Table 10) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =1.7V, fc = 400kHz (rise/fall time < 30ns) During tW, 1.7V < VCC < 2.5V VIN = VSS or VCC, 1.7V < VCC < 2.5V -0.45 0.7VCC IOL = 0.7 mA, VCC = 1.7 V Min. Max. Unit
ILI ILO ICC ICC0 ICC1 VIL VIH VOL
Input Leakage Current (SCL, SDA, E2, E1, E0) Output Leakage Current Supply Current (Read) Supply Current (Write) Stand-by Supply Current Input Low Voltage (SDA, SCL, WC) Input High Voltage (SDA, SCL, WC) Output Low Voltage
2 2 0.8 3(2) 1 0.3 VCC VCC+1 0.2
A A mA mA A V V V
1. Preliminary data. 2. Characterized value, not tested in production.
24/34
M24128, M24C64, M24C32 Table 17.
DC and AC parameters
AC characteristics (VCC = 2.5V to 5.5V, device grades 6 and 3)
Test conditions specified in Table 11 and Table 8
Symbol fC tCHCL tCLCH tDL1DL2(1) tDXCX tCLDX tCLQX tCLQV
(2)
Alt. fSCL tHIGH tLOW tF Clock Frequency
Parameter
Min.
Max. 400
Unit kHz ns ns
Clock Pulse Width High Clock Pulse Width Low SDA Fall Time
600 1300 20 100 0 200 200 600 600 600 1300 5 900 300
ns ns ns ns ns ns ns ns ns ms
tSU:DAT Data In Set Up Time tHD:DAT Data In Hold Time tDH tAA Data Out Hold Time Clock Low to Next Data Valid (Access Time)
tCHDX(3) tDLCL tCHDH tDHDL tW
tSU:STA Start Condition Set Up Time tHD:STA Start Condition Hold Time tSU:STO Stop Condition Set Up Time tBUF tWR Time between Stop Condition and Next Start Condition Write Time
1. Sampled only, not 100% tested. 2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. For a reSTART condition, or following a Write cycle.
Table 18.
AC characteristics (VCC = 1.8V to 5.5V or VCC = 1.7V to 5.5V)
Test conditions specified in Table 11 and Table 9 or Table 10
Symbol fC tCHCL tCLCH tDL1DL2
(1)
Alt. fSCL tHIGH tLOW tF Clock Frequency
Parameter
Min.
Max. 400
Unit kHz ns ns
Clock Pulse Width High Clock Pulse Width Low SDA Fall Time
600 1300 20 100 0 200 200 600 600 600 1300 10 900 300
ns ns ns ns ns ns ns ns ns ms
tDXCX tCLDX tCLQX tCLQV(2) tCHDX(3) tDLCL tCHDH tDHDL tW
tSU:DAT Data In Set Up Time tHD:DAT Data In Hold Time tDH tAA Data Out Hold Time Clock Low to Next Data Valid (Access Time)
tSU:STA Start Condition Set Up Time tHD:STA Start Condition Hold Time tSU:STO Stop Condition Set Up Time tBUF tWR Time between Stop Condition and Next Start Condition Write Time
1. Sampled only, not 100% tested. 2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. For a reSTART condition, or following a Write cycle.
25/34
DC and AC parameters Figure 12. AC waveforms
tCHCL tCLCH
M24128, M24C64, M24C32
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid
AI00795C
tCLQX
26/34
M24128, M24C64, M24C32
Package mechanical
8
Package mechanical
Figure 13. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, package outline
b2 A2 A1 b e eA D
8
E A L c eB
E1
1 PDIP-B
1. Drawing is not to scale.
Table 19.
Symbol
PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, package mechanical data
millimeters Typ. Min. Max. 5.33 0.38 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.30 2.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. inches Min. Max. 0.210
A A1 A2 b b2 c D E E1 e eA eB L
27/34
Package mechanical
M24128, M24C64, M24C32
Figure 14. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 20.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data
millimeters inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 - 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 - 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
28/34
M24128, M24C64, M24C32
Package mechanical
Figure 15. TSSOP8 - 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 21.
Symbol
TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data
millimeters Typ. Min. Max. 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. inches Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1
29/34
Package mechanical
M24128, M24C64, M24C32
Figure 16. UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale.
Table 22.
UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package mechanical data
millimeters inches Max 0.60 0.05 0.30 2.10 1.70 0.08 3.00 0.20 0.50 0.45 2.90 0.10 - 0.40 3.10 0.30 - 0.50 0.15 0.30 0.012 0.118 0.008 0.020 0.018 0.114 0.004 - 0.016 Typ 0.022 0.001 0.010 0.079 0.063 Min 0.020 0.000 0.008 0.075 0.059 Max 0.024 0.002 0.012 0.083 0.067 0.003 0.122 0.012 - 0.020 0.006
Symbol Typ A A1 b D D2 ddd E E2 e L L1 L3 0.55 0.02 0.25 2.00 1.60 Min 0.50 0.00 0.20 1.90 1.50
30/34
M24128, M24C64, M24C32
Part numbering
9
Part numbering
Table 23.
Example: Device Type M24 = I2C serial access EEPROM Device Function 128-B = 128 Kbit (16384 x 8) C64- = 64 Kbit (8192 x 8) C32- = 32 Kbit (4096 x 8) Operating Voltage W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V F = VCC = 1.7 to 5.5V(1) Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MB = UFDFPN8 (MLP8)(2) Device Grade 6 = Industrial: device tested with standard test flow over -40 to 85 C 3 = Automotive: device tested with High Reliability Certified Flow(3) over -40 to 125C. 5 = Consumer: device tested with standard test flow over -20 to 85C(1) Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P or G = ECOPACK(R) (RoHS compliant) Process B = F6DP26% Rousset P = F6DP26% Chartered
1. Device grade 5 is available only with the operating voltage option F. 2. The UFDFPN8 package is available in M24C32-x devices only. It is not available in M24C64-x devices. 3. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
Ordering information scheme
M24C32- W MN 6 T P /B
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of Second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
31/34
Revision history
M24128, M24C64, M24C32
10
Revision history
Table 24.
Date 22-Dec-1999 28-Jun-2000 31-Oct-2000
Document revision history
Revision 2.3 2.4 2.5 Changes TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData). TSSOP8 package data corrected References to Temperature Range 3 removed from Ordering Information Voltage range -S added, and range -R removed from text and tables throughout. Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated References to PSDIP changed to PDIP and Package Mechanical data updated Test condition for ILI made more precise, and value of ILI for E2-E0 and WC added -R voltage range added Document reformatted using new template. TSSOP8 (3x3mm body size) package (MSOP8) added. 5ms write time offered for 5V and 2.5V devices SO8W package removed. -S voltage range removed TSSOP8 (3x3mm body size) package (MSOP8) removed Table of contents, and Pb-free options added. Minor wording changes in Summary Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. VIL(min) improved to -0.45V. Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature information clarified for RoHS compliant devices. Device Grade clarified Product List summary table added. Device Grade 3 added. 4.5-5.5V range is Not for New Design. Some minor wording changes. AEC-Q100002 compliance. tNS(max) changed. VIL(min) is the same on all input pins of the device. ZWCL changed. UFDFPN8 package added. Small text changes.
20-Apr-2001
2.6
16-Jan-2002
2.7
02-Aug-2002 04-Feb-2003 27-May-2003 22-Oct-2003
2.8 2.9 2.10 3.0
01-Jun-2004
4.0
04-Nov-2004
5.0
05-Jan-2005
6.0
32/34
M24128, M24C64, M24C32 Table 24.
Date
Revision history
Document revision history (continued)
Revision Changes Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added. Section 2.1: Chip Enable (E0, E1, E2) and Section 2.2: Write Control (WC) modified, Section 2.3: Supply voltage (VCC) added and replaces Power On Reset: VCC Lock-Out Write Protect section. TA added, Note 1 updated and TLEAD specified for PDIP packages in Table 7: Absolute maximum ratings. ICC0 added, ICC voltage conditions changed and ICC1 specified over the whole voltage range in Table 13: DC characteristics (VCC = 2.5V to 5.5V, device grade 6). ICC0 added, ICC frequency conditions changed and ICC1 specified over the whole voltage range in Table 15: DC characteristics (VCC = 1.8V to 5.5V). tW modified in Table 17: AC characteristics (VCC = 2.5V to 5.5V, device grades 6 and 3). SO8N package specifications updated (see Figure 14 and Table 20). Device grade 5 added, B and P Process letters added to Table 23: Ordering information scheme. Small text changes. ICC1 modified in Table 13: DC characteristics (VCC = 2.5V to 5.5V, device grade 6). Note 1 added to Table 16: DC characteristics (VCC = 1.7V to 5.5V) and table title modified. UFDFPN8 package specifications updated (see Table 22). M24128-BWand M24128-BR part numbers added. Generic part number corrected in Feature summary on page 1. ICC0 corrected in Table 14 and Table 13. Packages are ECOPACK(R) compliant.
29-Jun-2006
7
03-Jul-2006
8
17-Oct-2006
9
33/34
M24128, M24C64, M24C32
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